International workshop on Code Optimisation for Multi and many Cores
会议地点: Washington D.C., USA
Many-core architectures, such as mobile SOCs, GPGPUs, and deep learning accelerators, are quickly becoming the norm in computing devices and consumer electronics. While essential for high performance under the power and thermal constraints we face, programmers still struggle with using them efficiently. Which code can be parallelized profitably, which parallel patterns to use to implement the algorithm, how to map it optimally to the available hardware? Many-cores will provide high performance and energy efficiency only when we make the right decisions for these problems.
With novel research papers and expert invited speakers from both industry and academia, this workshop aims at examining different solutions to these problems and includes (but is not limited to):
- programming languages and models
- compilers and tools
- runtime systems
- operating systems
- binary translation
- combinations of the above
for homogeneous, heterogeneous multi-core and many-core based systems.